1. Field of the lnvention:
This invention relates to a method of fabricating an inter-layer dielectric (ILD) for a salicide process, and more particularly, to a method of fabricating a crack resistant ILD for a salicide process.
2. Description of Related Art:
Because of semiconductor device line width and pattern downsizing, the conductivity of the polysilicon gate of a metal-oxide-semiconductor (MOS) device and the wiring line of a semiconductor device is lowered. A gate includes one or more metal or salicide layers formed on top of a polysilicon layer. Compared with a gate containing only polysilicon, the foregoing gate has a lower resistance. A salicide gate is fabricated by forming a salicide layer, such as a titanic silicide, with a thickness of about 1000.ANG., to cover a polysilicon layer, with a thickness of about 1000 to 3000.ANG., wherein the salicide layer provides a horizontal conducting path with a lower resistance above the gate.
Because the existence of an ILD layer is to prevent an electric short circuit between the gate and the metal layer, which is formed by a follow-up sputtering process, normally, a relatively thick insulating layer is formed on the gate, to be used as an ILD layer after the gate is formed, to insulate both the gate and the metal layer. After the formation of the ILD layer, the follow-up patterning process is performed to form the contact hole.
FIGS. 1A through 1C are sectional views showing a conventional method of fabricating a crack resistant ILD for a salicide process. Referring to FIG. 1A, gate oxide 102 and polysilicon layers 104a and 104b, which are used as gates, are formed on the substrate 100. Then, before the formation of spacer 106, a light ion implantation is performed on the substrate 100. After the spacers 106 are formed on the sides of the gate 104a and 104b, heavy ion implantation is performed on the substrate 100 to form lightly doped drain (LDD) regions 108. A thermal process is performed to form a titanium layer on the substrate 100. This titanium layer reacts with the substrate 100 and the polysilicon used as gates 104a and 104b, to form titanium silicide 110a and 110b on the lightly doped drain regions 108, and gates 104a and 104b. A insulating layer 112, such as a non-doped silicon oxide layer, is formed on the substrate 100 to cover the gates 104a and 104b, and the substrate 100 after the rest of the titanium layer is removed from the substrate 100.
Referring to FIG. 1B, an ILD layer is formed on the substrate 100, wherein the formation of the ILD layer includes first forming a borophosphosilicate glass (BPSG) layer 114a on the insulating layer 112. This is followed by forming a spin-on glass (SOG) layer 114b on the BPSG layer 114a, and performing a chemical-mechanical polishing process. The SOG layer is used to fill the dish locations and holes on the surface of the BPSG layer to improve planarity. Then, a patterning process is performed form a contact hole 116 which is electrically connected to the lightly doped regions 108.
Because natural oxide is formed on the bottom surface of the contact hole 116, an extra process for removing the native oxide using chemical etching liquid is required before the metal sputtering process is carried out. However, the ILD layer 114a and insulating layer 112 are very easily damaged by the chemical etching liquid. Once the ILD layer 114a is damaged by the chemical etching liquid, the chemical etching liquid further damages the insulating layer 112 and the spacers 106 through the cracks 120 within the ILD layer 114a. As a result, the metal layer 118, which fills the contact hole 116 in the follow-up fabrication process also fills the cracks 120, creating bridges between gates 104a and 104b, which cause short circuits and abnormal currents.